Education:
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- InDesign CS2 (2005)
- HTML, XML (2005)
- HTML 4.0 CSS and Frames, update (2003)
- C++ Training (update from C) (2003)
- FLASH 5.0 Training - FLASH Animation for eLearning for Advanced Chip Synthesis and Introduction to Static Timing Analysis (2002)
- Chip Architect, Physical Compiler, PrimeTime, 2001 Update Training (Design Compiler and vairations of it) , Design Vision, Chip Synthesis, Advanced Chip Synthesis, Module Compiler, Design Compiler, TetraMax, Dreamweaver (1998-2002).
- Professional seminars on Cadence's HDL Floorplanner, Candence's Gate Ensemble, Silicon Ensemble and Synopsys' Design Compiler (chip synthesis), continued training in HTML/web design (1997-1998)
- Professional Certificate in Marketing Communications , UCSD, 1994. Ceremony June 24, 1996
- Extension credits, UCSD, in writing, screen writing, 1994
- Ph.D. in Computer Science, UCLA, 1974 (Also worked on a PhD in Engineering - Computer-Assisted Instruction - all but the thesis)
- Master's degree in Engineering (MSEE in Information Theory),UCLA, March 1969
- Extension credits, UCLA, in French, art, transistor theory 1967-1969
- BSEE (Electrical Engineering), University of Hartford, Connecticut, June 1964
- ASE (Electrical Engineering), University of Hartford, Connecticut, June 1962
- Scientific College Preparatory Degree , Norwich Free Academy, Connecticut, June 1960
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Thesis and Research
- Doctoral Thesis
- UCLA
Fault Detection Through Parallel Processing in Boolean Algebra
Chairman, Dr. Antonin Svoboda, Professor Emeritus, UCLA
Secondary research in Computer Applications in Education (CAI and other
applications)
- Master's Thesis
- UCLA
Investigation and Evaluation of General Purpose Digital Computer
Circuit Design/Analysis Programs (A User's Guide for ECAP, CIRCUS, SCEPTRE
and NASAP). Published on a restricted basis.
Chairman, Professor Lawrence P. McNamee, UCLA
- Undergraduate
Thesis - Uof Hartford, CT
A Study of Transients
Chairman, Professor Carl Alsing, University of Hartford
Publications
Dr. White has authored
over 40 technical papers, seminars and monographs on ASIC-based Logic
Design, CAD Modeling, Fault Detection, Boolean Logic, Bit-Slice Design
and Structured Microprogramming.
She is the author
of the following hard-cover texts:
Other technical publications
Articles, Papers
and Reports Published
- White, Donnamaie
E. "Stalked by Analog Design", Computer Design, January
1997, pg 40.
- White, Donnamaie
E. "Firmware Level Interrupts for the 2900 ", Digital
Design, March 1981, pp. 76-77.
- "Bit-Slice
Design: The Am2910", University of Santa Clara, Seminar
Notes, 1979
- Svoboda, A., D.
E. White "Advanced Logical Circuit Design Techniques Seminar
Notes ", UCLA, February 1977.
- Fault Detection
Through Parallel Processing in Boolean Algebra Ph.D. Thesis, Chairman,
Dr. Antonin Svoboda, Professor Emeritus, UCLA, Published as UCLA-ENG-7504,
1975. 157 pages.
- White, Donnamaie
E., and Antonin Svoboda "Fault Detection in Combinational Circuits:
The Test Sequence", Proceedings of the Eighth Asilomar Conference
on Circuits, Systems and Computers, December 3-5, 1974, Pacific
Grove, CA. (Published).
- "Test
Sequence Alternative to Fault Detection", Seminar Notes,
Cal Poly, October 1974.
- Investigation
and Evaluation of General Purpose Digital Computer Circuit Design/Analy
sis Programs (A User's Guide for ECAP, CIRCUS, SCEPTRE and NASAP)
. MSEE Thesis, Published on a restricted basis. Chairman, Professor
Lawrence P. McNamee, UCLA
- Martin, D. F.,
L. P McNamee, D. E. Meyerhoff, T. S. Chow "Standardization and
Qualification of Computer Programs for Circuit Design". UCLA-ENG-7087
, September 1970. (NASA Tech Brief filed in 1972, B72-10142, Marshall
Space Flight Center. Received the NASA Certificate of Recognition for
this brief in October, 1973.)
- Meyerhoff, D.
E., L. P. McNamee "An Evaluation of the Numerical Significance
of General Circuit Analysis Programs in Relation to the Transient Problem".
Second Hawaii Conference on System Sciences. Presented during January,
1969. Proceedings, pp. 565-573.
- Meyerhoff, D.
E., Lawrence P. McNamee "Connsiderations for Optimum CGA Program
Appli cations". Sixth Annual Allerton Conference on Circuit
and System Theory . Presented during October 2-4, 1968. Proceedings,
pp. 396-405.
- Meyerhoff, Donnamaie
Eileen "Computer Applications: Circuit Analysis". Fifth
Annual Allerton Conference on Circuit and Systems Theory , presented
during October 4-6, 1967, Proceedings, pp 513-520.
- Meyerhoff, D.
E. "Modeling for Computer Aided Circuit Design/Analysis Programs:
Part I. CAD Program Transistor Models, A Survey". Appendix
B, UCLA, Department of Engineer ing Report 68-38, 1968.
- Meyerhoff, D.
E. "Modeling for Computer Aided Circuit Design/Analysis Programs:
Part II. CAD Program Transistor Models for Hostile (Weapon) Environment
Effects". Ibid.
Corporate Publications
- Advanced Chip
Synthesis eLearning Demo
- eADVCHP - Advanced
Chip Synthesis - eLearning Project Coordinator - on-line training class
- Web-Based Training
Video on Design Vision,(Squared Circle) 2/2001
- CHIP Synthesis
Workshop and Labs 2/2001
- Advanced CHIP
Synthesis Workshop and Labs 12/2000
- Author of the
Internal Technical Training internal home pages
- CBA Design System
Workshop (1997-1998)
- Author of the
growing IMP web structure, as well as editor of EPAC datasheets, manuals,
application notes and application briefs. 1995-1997
- EPAC Design Handbook,
4/96
- EPAC User's Manual,
April 1995, November 1996
Author of the AMCC internal home pages with interconnected web structure
of marketing materials.
- Logic Design for
Array-Based Circuits Seminar and Notes
- Q20000 Design
manual
- MacroMatrix Reference
Manual
- Q20000 Rapid
Reference Guide and Design Rules
- User Guides and
manuals for Daisy Logician, Mentor, Valid design systems using AMCC
software (several)
- Q24000 BiCMOS
design manual
- Q24000 Rapid
Reference Guide and Design Rules
- Q14000 CMOS Design
Manual
- Q9000 and Q6000
CMOS Design Manuals
- Q5000 Bipolar
Design Manual
- Q3500 Bipolar
Design Manual
- Q1500/ QH1500
Bipolar Design Manual
- Q700 Bipolar
Design Manual
Author of the AMD
seminars
- Bit-Slice Design:
Controllers and ALUs
- Development System
29
- Microprogrammable
Computer Architecture
- Trace 29
and editor of the
courses
- Zilog processor
- C Programming
Language
- and related classes
for the Zilog development system.
Current Work Experience
- SanDisk in Sunnyvale April 3, 2006 - Manager ASIC Technical Publications, Working on document control and other related process issues
- Currently working on Bit-Slice Design: Controllers, ALUs and Microcode eBook, to be released 2006 to WhitePubs.com
Websites Authored and Maintained
- Corporate and eLearning
Older Websites - Other
eLearning Sites
- impinc.com - designed
the company's original site - maintained it for three years (1995-1998)
- tensilica.com
- design the company's original website (1999)
- amcc.com - internal
website - ASIC Design Class (Design for Array-Based Circuits) - first
eLearning site (HTML 1.0) (1995)
- synopsys.com -
internal site - CBA Design System - eLearning (HTML 3.0) (1997-1999)
- TroySutter.com
- currently removed from the web (cover Model and extreme bartender)
(2000)
Work History
- SunDisk in Sunnyvale April 3, 2006 - Sr. Technical Writer/Content Developer
- WhitePubs.com in San Diego, CA August 2005 - ongoing - Bit-Slice Design: Sequencers, Controllers, ALUs and Microcode; eBook (to be published 2006)
- Micron Technology in San Jose, October 2004 - August 10, 2005 Manager Imaging Technical Publications, Datasheet, technical notes, Imaging products; methodology for documentation process.
- PLX Technology in San Jose November 2003 - October 2004 Technical Writer/Content Developer Independent Contractor PCI PCI-X and PCI Express Bridges
- QuickSilver Technology in San Jose. July 2002 - July 31, 2003
Lead Technical Writer/content developer, Programmer's Guides and Assembly
Language Reference Manauls for the QuickSliver Technology Adaptive Computing
Machine (ACM) nodes and architecture (Adaptable microprocessor devices
targeted to the mobile wireless industry). Consultant on controller
design. Also: debug - Assemblers, Simulators, Validation plans, Syntax
and semantic definitions; sample code; MarCom support.
Synopsys (4/1997-3/2002)
- eLearning Project
Coordinator - Advanced Chip Synthesis
- Sr. Content Developer/Sr.
Staff Instructor - CD Department, ETS, Synopsys, 10/1999- 2000. Lead
Developer, Advanced Chip Synthesis Workshop(2000), Lead Developer, Chip
Synthesis Workshop, (2001), CD Rep for Development - Chip Architect,
Advanced Chip Synthesis, Chip Synthesis workshops, 2001; WBT (Web Based
Training) Tiger Team.
- Sr. Education
Developer/Webmaster, Internal Technical Training, ETS, Synopsys, 10/98
- 10/99 Assigned to the DTG group (Design Compiler) -
- Technical Training
Manager, Silicon Architecture (SIARC), Synopsys, 4/97-10/98 CBA Design
System Software, design tools and utilites for design entry, synthesis,
simulation, timing verification, place and route and physical verification.
- Technical Publications
Manager, IMP. Inc. (March 1995 -April 1997 ) and Creative Webmaster
for the IMP web site (http://www.impweb.com) (3/95-1/98). Responsible
for technical documentation and marketing sup port for the IMP EPAC
project, including:
- Editor of
The EPAC Design Handbook (1996)
- writing the
user's manual for the IMP50E10 Development System and Analog Magic
1.2 the development system software
- writing and
editing application briefs and application notes packaging the development
system marketing literature (registration, license, customer letter,
release notes)
- creating
presentations and player files.
- creating,
maintaining and monitoring the IMP web site.EPAC User's Guide including
Analog Magic, April 1995.
- Director of Market
Communication at AMCC in San Diego (3.5 years) and the Director of Customer
Documentation and Training at AMCC (10 years, overlapping above), 1984-1995.
Director of Market
Communications for AMCC in San Diego (1990-1994). Developed and coordinated
the marketing for three business units and the corporation including
advertising, direct mail (design and copywriting), inquiry handling
and response packages, the inquiry database, com pany letterhead,
business cards, press packages (look and content), press releases,
player files for trade shows, presentations, datasheets, trade show
booths, databooks, design manuals, field/customer news letters, product
introduction and announcements.
Director of Customer
Documentation and Training, AMCC, 1984-1990. Developed the design
methodology, from design conception through design submission procedures,
for the all of the AMCC logic array families, High-Speed Bipolar,
CMOS, and BiCMOS, including the specification of most of the MacroMatrix
design support software. This included the design and coding of the
more complex algo rithms, debug and documentation. Authored the AMCC
Array Design Manuals (Q700, Q1500, Q3500, Q5000, Q20000 Bipolar and
Q9000, Q14000 BiCMOS) and the User's Manuals for the design support
software (rules, checks, vector submission, vector checking, design
checklist, package selection, anno tation).
- Extension Lecturer
in Computer Science at UCSD, Logic Design for Array Based Circuits,
offered at various times between 1984 and 1994.
- Principal Engineer
on staff for two years (1982-1984) at the Raytheon Computer and Displays lab in Sudbury, Mass. Responsible for the development of the structured
microprogramming techniques to be used by Raytheon, and the supervision
of the microprogramming teams for systems under development.
While at Raytheon,
Responsible for the coordination of three micro code development teams
(16 people, three micro engines) and the development of the microcode
for the militarized VAX emulation. Designed and developed a database
program to generate all 42 management reports following weekly reviews.
Developed the
structured microprogramming specification for Raytheon projects and
established the standards for all future projects of a like nature.
- Director of Customer
Training for Advanced Micro Devices (AMD)/Advanced MicroComputers
(AMC) for four years (1978-1982) Authored over 40 technical papers on
CAD modeling, fault detection, Boolean logic, Bit-Slice Design and microprogramming.
Developed and documented the design methodology for structured bit-slice
design and microprogramming for the AMD2900 bit-slice series while heading
customer training and the AMD applications documentation center.
Included: creating
the department (a P/L center), designing curriculum, creating the
seminars, staffing, budgeting, demand forecast, lab equipment set-up,
sales training, developing a publication support operation and writing
25 of 30 publications available. Designed and decorated the Customer
Training Center.
- University of
Santa Clara, CA. Guest Lecturer Early-Bird Program . Taught Bit-Slice
Design. 1979.
- Telefile Computer
Products, Inc., Irvine, CA. Director of Engineering Responsibilities
included the supervision and direction of engineering, drafting and
software development personnel. Coordinated support of the production
and test departments and provided interface and support to field service
and marketing personnel. Left to join AMD. April 1977- April 1978.
- Burroughs Western
Applications Development Center, Irvine, CA (WADC) Product Manager FORTE/2
database maintenance, Senior Systems Analyst, Audit Reporter development.
Supervisor: Art Sommerville. December 1975 - April 1977.
- Burroughs Corporation, Pasadena, CA Senior Programming Specialist Project leader for MS-3 S-code
assembler; R and D for firmware language; did initial design of I/O
system microproces sor hardware and language; worked on the LCP card
reader debug; wrote test programs for LCPs. July 1974 - December 1975.
- California State
University, Fullerton. Lecturer, School of Business Administration and
Eco nomics, Department of Quantitative Methods. Taught Probability,
Statistics, Elementary Operations Research, Programming (FORTRAN, COBOL,
BASIC, ALGOL, PL/1, LISP, TRAC, GPSS {all on a CDC-3150} , APL {on IBM
System/370}) Chairman: Dr. Stanton. September 1971-June 1974.
- California State
University, Los Angeles. Associate/Assistant Professor, School of Business.
Taught Introduction to Computer Programming (COMPASS, FORTRAN, COBOL)
Summers, 1971, 1972. Taught Introduction to Logic Design, Intermediate
Logic Desing and Advanced Logic Design.
- California State
University, Northridge. Lecturer, School of Business Taught Introduction
to the COBOL Programming Language, Introduction to the FORTRAN Programming
Language. Sep tember 1970-June 1971 (part time)
- University of California, Los Angeles U. Reader October 1969-March 1970 (part time)
- Northrop Corporate
Labs, Hawthorne, CA. Member of the Technical Staff. Did research in
the development of transistor models for hostile (weapon) environments.
Supervisor: J. Raymond. April 1968-August 1969.
- TRW Systems Group,
One Space Park, Redondo Beach, CA Member of the Technical Staff With
the Digital Circuits Development Section of the Electronics Systems
Lab., was primarily engaged in design review and computer-aided circuit
analysis (Minuteman, LEM, etc.) January 1966 - March 1968. Supervisor:
L. Glassmaker.
- Pacific Telephone
Company, 740 S. Olive Street, Los Angeles, CA Equipment Engineer Assigned
as an equipment engineer, information services, primarily engaged in
call density forecasts, liaison to Bell Labs for development of a computer-controlled
call distribution office (Century City), short and long range equipment
installation planning, evaluation of office performance. July 1964 -
January 1966.
Teaching Record
- Web-Based
Training Video and presentation - Design Vision (Design Compiler GIU),
Internal Training Only, Synopsys, 2000
- Advanced
Chip Synthesis (Synopsys Design Compiler - and Design Flow), Synopsys,
2000
- Effective
Training Skills, bring adult education theory to technical training,
Synopysy, 1999
- CBA
Design System, a structured methodology for ASICs using the Synopsys
CBA library, Design Compiler and Gate Ensemble (from Cadence), taught
at Synopsys, 1997-1999
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Introduction to the Internet and IMP's Web SIte, February, 1996 IMP
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Logic Design for Array-Based Circuits UCSD, AMCC (1984-last time Dec.
1994)
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Introduction to Logic Design, Cal State LA
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Intermediate Logic Design, Cal State LA
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Advanced Logic Design, Cal State LA
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Advanced Logic Circuit Design Techniques, UCLA 1977
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Structured Microprogramming, AMD
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Bit-slice design: Controllers and ALUs (Structured Design) U Santa Clara,
AMD (1978-1982)
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Advanced Microprogrammable Computer Architectures, AMD
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the AmZ8000, AMD
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Data Processing, Cal State Fullerton, Cal State LA
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On-Line Computers (Business Computing), Cal State Fullerton
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Probability and Programming (BASIC), Cal State Fullerton
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Statistics, Cal State Fullerton
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Searching Algorithms (Database), Burroughs
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The C Programming Language, AMD
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Pascal language, AMD
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Operating Systems - Overview, AMD (on the beach at a Sales Conference)
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AMDASM microprogramming language, AMD
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AmSYS29 development system for microprogram debug, AMD
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AmSYS8 development system, AMD
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Comparative Compiler Theory (BASIC, FORTRAN, COBOL, ALGOL, PL/1, LISP,
GPSS, TRAC, AP/L), Cal State Fullerton
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Introduction to COBOL, Cal State Northridge
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Introduction to FORTRAN, Cal State Northridge
References
Available on request
Research Record
While at both TRW
and Northrop Corporate Labs I was assigned to hostile weapon effects analysis
(classified). The non-classified part of the work appeared in several
papers and was used as part of my Master's Thesis. Simply, it concerned
the reactions of circuits and components to beta surges and the design-stability
methodology required to prevent circuit failure. This was related both
to space -born weapons and the budding space program.
While at UCLA, I
did work on Svoboda's Triadic Graphical Calculus and his other theorems
related to digital logic design. I worked on one Ph.D. Thesis in Computer-Assisted
Instruction and prepared a seminar to introduce this (early '70s). I switched
thesis subjects and completed my Ph.D. using the Triadic Calculus and
Svoboda's Boolean Analyzer. My post-doctoral reaearch was with Svoboda,
working to present both a seminar and prepare a book ( Advanced Logic
Circuit Design Techniques) which would capture at least part of his work.
I have a completed
manuscript from Svoboda which has not been published. It is designed for
com puter-assisted instruction (cells and cross-reference linkage) that
is immediately suitable for publica tion on the Web. I would like to find
a University site to house this item. This book documents his life's work
on logic design theory. I have been watching the evolution of the technology
and believe HTML-based pages will be suitable.
At AMD, I developed
a structured firmware design methodology for the bit-slice devices and
at Raytheon I had the opportunity to apply it to a real-time multi-microcode-engine
system develop ment. This work was partially represented in the text Bit-Slice
Design: Controllers and ALUs.
At AMCC, I chaired
a multi-department taskforce to design and perfect a design methodology
for first-time silicon correctness. This involved identifying the design
algorithms that could automate the known design rules, developing new
rules and guidelines and perfecting the required design submis sion procedures.
As chairman, I was an algorithm designer, performed debug, documented
the process, developed the customer documentation and designed the customer
interface in addition to teaching the design seminar. Some of this work
is represented in the text Logic Design for Array Based Circuits.
Also while at AMCC,
I served on the grant request committee for Jerabek Elementary school
to help procure funding for computers in the classroom (1988). I served
on the grant review board for the department of education for one year.
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